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CAT4103 3-Channel Constant-Current RGB LED Driver
Description
The CAT4103 is a 3-channel, linear based constant-current LED driver designed for RGB LED control, requiring no inductor and provides a low noise operation. LED channel currents up to 175 mA are programmed independently via separate external resistors. Low output voltage operation of 0.4 V at 175 mA allows for more power efficient designs across wider supply voltage range. The three LED pins are compatible with high voltage up to 25 V supporting applications with long strings of LEDs. A high-speed 4-wire 25 MHz serial interface controls each individual channel using a shift register and latch configuration. Output data pins allow multiple devices to be cascaded and programmed via one serial interface with no need for external drivers or timing considerations. The device also includes a blanking control pin (BIN) that can be used to disable all channels independently of the interface. Thermal shutdown protection is incorporated in the device to disable the LED outputs whenever the die temperature exceeds 150C. The device is available in a 16-lead SOIC package.
Features
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SOIC-16 V SUFFIX CASE 751BG
PIN CONNECTIONS
GND BIN LIN SIN CIN RSET3 RSET2 RSET1 (Top View) 1 VDD BOUT LOUT SOUT COUT LED1 LED2 LED3
* 3 Independent Current Sinks Rated to 25 V * LED Current to 175 mA per Channel Set by Separate External * * * * * * * *
Resistors High-speed 25 MHz 4-wire Serial Interface Buffered Output Drivers to Ensure Data Integrity Cascadable Devices Low Dropout Current Source (0.4 V at 175 mA) 3 V to 5.5 V Logic Supply Thermal Shutdown Protection 16-lead SOIC Package These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS Compliant
MARKING DIAGRAM
L4A CAT4103VB YMXXXX
Applications
* Multi-color, Intelligent LED, Architectural Lighting * High-visual Impact LED Signs and Displays * LCD Backlight
L = Assembly Location 4 = Lead Finish - NiPdAu A = Product Revision (Fixed as "A") CAT4103V = Device Code B = Leave Blank Y = Production Year (Last Digit) M = Production Month (1-9, A, B, C) XXXX = Last Four Digits of Assembly Lot Number
ORDERING INFORMATION
Device CAT4103V-GT2 (Note 1) Package SOIC-16 (Pb-Free) Shipping 2,000/ Tape & Reel
1. Lead Finish NiPdAu
(c) Semiconductor Components Industries, LLC, 2010
March, 2010 - Rev. 1
1
Publication Order Number: CAT4103/D
CAT4103
VIN 5 V to 25 V VDD 3 V to 5.5 V C1 1 mF VDD BIN CONTROLLER LIN SIN CIN GND RSET1 R1 RSET2 R2
RED LED1
GREEN LED2
BLUE LED3 BOUT
CAT4103
LOUT SOUT COUT RSET3 R3
NEXT CAT4103 DEVICE
Figure 1. Typical Application Circuit
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter VDD Voltage Input Voltage Range (SIN, BIN, CIN, LIN) Output voltage range (SOUT, BOUT, COUT, LOUT) LED1, LED2, LED3 Voltage DC Output Current on LED1 to LED3 Storage Temperature Range Junction Temperature Range Lead Soldering Temperature (10 sec.) ESD Rating: All Pins Human Body Model Machine Model Rating 6 -0.3 V to VDD+0.3 V -0.3 V to VDD+0.3 V 25 200 -55 to +160 -40 to +150 300 2000 200 Units V V V V mA _C _C _C V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Table 2. RECOMMENDED OPERATING CONDITIONS
Parameter VDD Voltage applied to LED1 to LED3, outputs off Voltage applied to LED1 to LED3, outputs on Output Current on LED1 to LED3 Ambient Temperature Range Range 3.0 to 5.5 up to 25 up to 6 (Note 2) 2 to 175 -40 to +85 Units V V V mA _C
2. Keeping the LEDx pin voltage below 6 V in operation is recommended to minimize thermal dissipation in the package.
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CAT4103
Table 3. ELECTRICAL OPERATING CHARACTERISTICS (Min and Max values are over recommended operating conditions unless specified otherwise. Typical values are at VIN = 5.0 V, TAMB = 25C.)
Symbol DC CHARACTERISTICS IDD1 IDD2 IDD3 IDD4 ILKG RLIN RBIN VIH VIL IIL VOH VOL VRSET TSD THYS ILED/IRSET VUVLO Supply Current Outputs Off Supply Current Outputs Off Supply Current Outputs On Supply Current Outputs On LED Output Leakage LIN Pull-down Resistance BIN Pull-up Resistance SIN, BIN, CIN, LIN logic high level SIN, BIN, CIN, LIN logic low level Logic Input Leakage Current (CIN, SIN) xOUT Logic High Output Voltage xOUT Logic Low Output Voltage RSETx Regulated Voltage Thermal Shutdown Thermal Hysteresis RSET to LED Current Gain ratio Undervoltage Lockout (UVLO) Threshold 100 mA LED Current VI = VDD or GND IOH = -1 mA IOL = 1 mA VLED = 5 V, RSET = 24.9 kW VLED = 5 V, RSET = 5.23 kW VLED = 0.5 V, RSET = 24.9 kW VLED = 0.5 V, RSET = 5.23 kW VLED = 5 V, Outputs Off -1 140 140 0.7x VDD 0.3x VDD -5 VCC - 0.3 V 0.3 1.17 1.2 150 20 400 1.8 V 1.23 V C C 0 5 mA V 180 180 2 4 2 4 5 10 5 10 1 250 250 mA mA mA mA mA kW kW V Name Conditions Min Typ Max Units
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CAT4103
Table 4. TIMING CHARACTERISTICS (Min and Max values are over recommended operating conditions unless specified otherwise. Typical values are at VIN = 5.0 V, TAMB = 25C.)
Symbol CIN fcin tcwh tcwl SIN tssu tsh LIN Tlwh tlchd tlcsu LEDn tledplon tledploff tledpbon tledpboff tledr tledf SOUT tsr tsf tsdf tsdr COUT tcr tcf tcdf tcdr LOUT tlr tlf tldf tldr BOUT tbr tbf tbdf tbdr BOUT rise time (10% to 90%) BOUT fall time (90% to 10%) Propagation delay time BOUT Propagation delay time BOUT CL = 15 pF CL = 15 pF BIN falling to BOUT falling BIN rising to BOUT rising 5 5 6 8 20 20 ns ns ns ns LOUT rise time (10% to 90%) LOUT fall time (90% to 10%) Propagation delay time LOUT Propagation delay time LOUT CL = 15 pF CL = 15 pF LIN falling to LOUT falling LIN rising to LOUT rising 5 5 4 5 10 10 ns ns ns ns COUT rise time (10% to 90%) COUT fall time (90% to 10%) Propagation delay time COUT Propagation delay time COUT CL = 15 pF CL = 15 pF CIN falling to COUT falling CIN rising to COUT rising 5 5 4 4 10 10 ns ns ns ns SOUT rise time (10% to 90%) SOUT fall time (90% to 10%) Propagation delay time SOUT Propagation delay time SOUT CL = 15 pF CL = 15 pF CIN falling to SOUT falling CIN falling to SOUT rising 5 5 6 6 18 18 ns ns ns ns Turn on Propagation delay LIN Turn off Propagation delay LIN Turn on Propagation delay BIN Turn off Propagation delay BIN LED rise time (10% to 90%) LED fall time (90% to 10%) LIN to LED(n) on LIN to LED(n) off BIN to LED(n) on BIN to LED(n) off Pullup resistor = 50 W to 3.0 V Pullup resistor = 50 W to 3.0 V 380 130 380 130 160 140 ns ns ns ns ns ns LIN Pulse width Hold time LIN to CIN Setup time LIN to CIN 20 4 8 ns ns ns Setup time SIN to CIN Hold time SIN to CIN 4 4 ns ns CIN Clock Frequency CIN Pulse Width High CIN Pulse Width Low 18 18 25 MHz ns ns Name Conditions Min Typ Max Units
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CAT4103
1/fcin
CIN tssu tsh tcwl tcwh
SIN tsdf tsdr SOUT tlwd tlchd tlcsu
LIN
Figure 2. Timing Diagram A
tledploff
tledplon
LIN tledpboff
BIN tledpbon
LED(n)
Figure 3. Timing Diagram B
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CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
(VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25C unless otherwise specified.) 1.2 QUIESCENT CURRENT (mA) QUIESCENT CURRENT (mA) No Load 1.0 8.0
6.0
0.8
4.0
0.6
2.0
0.4
3.0
3.5
4.0
4.5
5.0
5.5
0
0
100
200 RSET CURRENT (mA)
300
400
INPUT VOLTAGE (V)
Figure 4. Quiescent Current vs. Input Voltage (ILED = 0 mA)
6.0 QUIESCENT CURRENT (mA) Full Load LED CURRENT (mA) 200 160 120 80 40 0
Figure 5. Quiescent Current vs. RSET Current
5.5
5.0
4.5
4.0
3.0
3.5
4.0
4.5
5.0
5.5
0
0.2
0.4
0.6
0.8
1.0
INPUT VOLTAGE (V)
LED PIN VOLTAGE (V)
Figure 6. Quiescent Current vs. Input Voltage (ILED = 175 mA)
200 160 120 80 40 0 200 160 LED CURRENT (mA) 120
Figure 7. LED Current vs. LED Pin Voltage
LED CURRENT (mA)
80 40 0
3.0
3.5
4.0
4.5
5.0
5.5
-40
0
40 TEMPERATURE (C)
80
120
INPUT VOLTAGE (V)
Figure 8. LED Current Change vs. Input Voltage
Figure 9. LED Current Change vs. Temperature
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CAT4103
TYPICAL PERFORMANCE CHARACTERISTICS
(VIN = 5 V, VDD = 5 V, C1 = 1 mF, TAMB = 25C unless otherwise specified.) 1.30 1.30
RSET VOLTAGE (V)
1.20
RSET VOLTAGE (V)
1.25
1.25
1.20
1.15
1.15
1.10
3.0
3.5
4.0
4.5
5.0
5.5
1.10 -40
0
40 TEMPERATURE (C)
80
120
INPUT VOLTAGE (V)
Figure 10. RSET Pin Voltage vs. Input Voltage
200 160 LED CURRENT (mA)
Figure 11. RSET Pin Voltage vs. Temperature
120 80 40 0
0
15
30 RSET (kW)
45
60
Figure 12. LED Current vs. RSET Resistor
Figure 13. BIN Transient Response
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CAT4103
Table 5. PIN DESCRIPTIONS
Name GND BIN LIN SIN CIN RSET3 RSET2 RSET1 LED3 LED2 LED1 COUT SOUT LOUT BOUT VDD Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ground Reference Blank input pin Latch Data input pin Serial Data input pin Serial Clock input pin LED current set pin for LED3 LED current set pin for LED2 LED current set pin for LED1 LED channel 3 cathode terminal LED channel 2 cathode terminal LED channel 1 cathode terminal Serial Clock output pin Serial Data output pin Latch Data output pin Blank output pin Device Supply pin Function
Pin Function GND is the ground reference pin for the entire device. This pin must be connected to the ground plane on the PCB. BIN is the blank input used to disable all channels. When low, all LED channels are enabled according to the output latch content. When high, all LED channels are turned off. This pin can be used to turn all the LEDs off while preserving the data in the output latches. LIN is the latch data input. On the rising edge of LIN, data is loaded from the 3-bit serial shift register into the output register latch. On the falling edge of LIN the data is latched in the output register and isolated from the state of the serial shift register. SIN is the serial data input. Data is loaded into the internal register on each rising edge of CIN. CIN is the serial clock input. On each rising CIN edge, data is transferred from SIN to the internal 3-bit serial shift register. RSET1 to RSET3 are the LED current set inputs. The current pulled out of these pins will be mirrored in the corresponding LED channel with a gain of 400.
LED1 to LED3 are the LED current sink inputs. These pins are connected to the bottom cathodes of the LED strings. The current sinks bias the LEDs with a current equal to 400 times the RSET pin current. For the LED sink to operate correctly, the voltage on the LED pin must be above 0.4 V. Each LED channel can withstand and operate with voltages up to 25 V. COUT is a driven output of CIN and can be connected to the next device in the cascade. SOUT is the output of the 3-bit serial shift register. Connect to SIN of the next device in the cascade. SOUT is clocked on the falling edge of CIN. LOUT is a driven output of LIN and can be connected to the next chip in the cascade. BOUT is a driven output of BIN and can be connected to the next chip in the cascade. VDD is the positive supply pin voltage for the entire device. A small 1 mF ceramic capacitor is recommended close to the pin.
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CAT4103
Block Diagram
LED1 LED2 LED3 1.2 V Ref Current Setting VDD CURRENT SINKS + Current Setting Current Setting BIN RSET1 RSET2 RSET3 BOUT
BLANK LATCH
LIN
L0
L1
L2 LOUT
SIN
SHIFT REGISTER CLOCK
S0
S1
S2
DQ CK
SOUT
CIN
COUT GND
Figure 14. CAT4103 Functional Block Diagram
Basic Operation The CAT4103 uses 3 independent current sinks to accurately regulate the current in each LED channel to 400 times the current sink from the corresponding RSET pin. Each of the resistors tied to the RSET1, RSET2, RSET3 pins set the current respectively in the LED1, LED2, and LED3 channels. Table 6 shows some standard resistor values for RSET and the corresponding LED current.
Table 6. RSET RESISTOR SETTINGS
LED Current [mA] 20 60 100 175 RSET [kW] 24.9 8.45 5.23 3.01
Tight current regulation for all channels is possible over a wide range of input and LED voltages due to independent current sensing circuitry on each channel. The LED channels have a low dropout of 0.4 V or less for all current ranges and supply voltages. This helps improve heat dissipation and efficiency over other competing solutions. Upon power-up, an under-voltage lockout circuit clears all latches and shift registers and sets all outputs to off. Once the VDD supply voltage is greater than the under-voltage lockout threshold, the device can be programmed. Pull-up and pull-down resistors are internally provided to set the state of the BIN and LIN pins to low current off state when not externally driven.
A high-speed 4-wire interface is provided to program the state of each LED channel ON or OFF. The 4-wire interface contains a 3-bit serial-to-parallel shift register (S0-S2) and a 3-bit latch (L0-L2). The shift register operates on a first-in first-out (FIFO) basis. The most significant bit S2 corresponds to the first data entered in from SIN. Programming the serial-to-parallel register is accomplished via SIN and CIN input pins. On each rising edge of the CIN signal the data from SIN is moved through the shift register serially. Data is also moved out of SOUT to the next device if programming more than one device on the same interface. On the rising edge of LIN, the data content of the serial to parallel shift register is reflected in the latches. On the falling edge of LIN, the state of the serial-to-parallel register at that particular time is saved in the latches and does not change regardless of the content of the serial to parallel register. BIN is used to disable all LEDs off at one time while still maintaining the data contents of the latch register. BIN is an active low input pin. When low the outputs reflect the data in the latches. When high the outputs are all high impedance (LEDs off). All 4-wire inputs have a corresponding output driver for cascaded systems (SOUT, COUT, LOUT, BOUT). These output buffers allow many CAT4103 drivers to be cascaded without signal and timing degradation due to long wire interconnections.
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CAT4103
Application Information
Cascading Multiple Devices
The CAT4103 is designed to be cascaded for driving multiple RGD LEDs. Figure 16 shows three CAT4103 drivers cascaded together. The programming data from the controller travels serially through each device. Figure 15 shows a programming example turning on the following LED channels: BLUE3, GREEN2 and RED1. The programming waveforms are measured from the controller to the inputs of the first CAT4103.
Figure 15. Programming Example
5V
C1 1 mF RED1 GREEN1 BLUE1 LED3 BOUT C AT4103 #1 LOUT SOUT COUT RSET3 R3 VDD LED1 LED2
C2 1 mF RED2 VDD LED1 BIN LIN SIN CIN GND RSET1 RSET2 R4 R5 C AT4103 #2 GREEN2 BLUE2 LED3 BOUT LOUT SOUT COUT RSET3 R6 LED2
C3 1 mF BIN LIN SIN CIN GND RSET1 RSET2 R7 R8 C AT4103 #3 RED3 VDD LED1 GREEN3 BLUE3 LED3 BOUT LOUT SOUT COUT RSET3 R9 LED2
CONTROLLER
BIN LIN SIN CIN GND RSET1 RSET2 R1 R2
Figure 16. Three Cascaded CAT4103 Devices
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CAT4103
Power Dissipation Recommended Layout
The power dissipation (PD) of the CAT4103 can be calculated as follows:
P D + (V DD I DD) ) S(V LEDN I LEDN)
where VLEDN is the voltage at the LED pin, and ILEDN is the associated LED current. Combinations of high VLED voltage or high ambient temperature can cause the CAT4103 to enter thermal shutdown. In applications where VLEDN is high, a resistor can be inserted in series with the LED string to lower PD. Thermal dissipation of the junction heat consists primarily of two paths in series. The first path is the junction to the case (qJC) thermal resistance which is defined by the package style, and the second path is the case to ambient (qCA) thermal resistance, which is dependent on board layout. The overall junction to ambient (qJA) thermal resistance is equal to:
q JA + q JC ) q CA
Bypass capacitor C1 should be placed as close to the IC as possible. RSET resistors should be directly connected to the GND pin of the device. For better thermal dissipation, multiple via can be used to connect the GND pad to a large ground plane. It is also recommended to use large pads and traces on the PCB wherever possible to spread out the heat. The LEDs for this layout are driven from a separate supply (VLED+), but they can also be driven from the same supply connected to VDD.
For a given package style and board layout, the operating junction temperature TJ is a function of the power dissipation PD, and the ambient temperature, resulting in the following equation:
T J + T AMB ) P D (q JC ) q CA) + T AMB ) P D q JA
When mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading", the resulting qJA is about 74C/W. For example, at 60C ambient temperature, the maximum power dissipation is calculated as follow:
P Dmax + (T Jmax * T AMB) (150 * 60) + + 1.2 W q JA 74
Figure 17. Recommended Layout
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CAT4103
PACKAGE DIMENSIONS
SOIC-16, 150 mils CASE 751BG-01 ISSUE O
SYMBOL A A1 b c E1 E D E E1 e h L 0.25 0.40 MIN 1.35 0.10 0.33 0.19 9.80 5.80 3.80 9.90 6.00 3.90 1.27 BSC 0.50 1.27 NOM MAX 1.75 0.25 0.51 0.25 10.00 6.20 4.00
PIN#1 IDENTIFICATION TOP VIEW
0
8
D
h
A
q
e
b A1 SIDE VIEW
L
c
END VIEW
Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012.
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CAT4103
Example of Ordering Information (Note 5)
Prefix CAT Device # 4103 Suffix V -G T2
Company ID (Optional)
Product Number 4103
Package V: SOIC
Lead Finish G: NiPdAu Blank: Matte-Tin
Tape & Reel (Note 7) T: Tape & Reel 2: 2,000 / Reel
3. 4. 5. 6. 7.
All packages are RoHS-compliant (Lead-free, Halogen-free). The standard plated finish is NiPdAu. The device used in the above example is a CAT4103V-GT2 (SOIC, NiPdAu, Tape & Reel, 2,000/Reel). For additional temperature options, please contact your nearest ON Semiconductor Sales office. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
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CAT4103/D

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